Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication

This paper concerns performance modeling of semiconductor manufacturing operations. More specifically, it focuses on queueing network models for an analysis of wafer fabrication facilities. The congestion problems that plague wafer fabrication facilities are described in general terms, and several years' operating data from one particular facility are summarized. A simple queueing network model of that facility is constructed, and the model is used to predict certain key system performance measures. The values predicted by the model are found to be within about 10% of those actually observed. These results suggest that queueing network models can provide useful quantitative guidance to designers of wafer fabrication facilities, and we discuss refinements and extensions of our elementary model that are likely to be important in other settings. However, an even more important benefit to be gained from queueing theory is the simple qualitative point that congestion and delay in wafer fabrication are caused by variability in the operating environment. To significantly reduce manufacturing cycle times, one must reduce that variability.