Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment

References

• Al-Sharaeh S., Wells B. E. A comparison of heuristics for list schedules using the Box-method and P-method for random digraph generation. Proc. 28th IEEE Southeastern Sympos. System Theory (1996) Baton Rouge, Louisiana:467–471Crossref, Google Scholar
• Altera (2004) . Altera Online Device Data Sheets http://www.altera.comGoogle Scholar
• Altera NIOS (2004) . http://www.altera.com/niosGoogle Scholar
• Ammons G., Ball T., Larus J. R. Exploiting hardware performance counter with flow and context sensitive profiling. Proc. ACM SIGPLAN Conf. Programming Language Design Implementation (1997) Las Vegas, Nevada:85–96Crossref, Google Scholar
• Ball T., Larus J. Efficient path profiling. Proc. IEEE/ACM Internat. Sympos. Microarchitecture Micro-29 (1996) Paris, France:46–57Crossref, Google Scholar
• Beck E., Siewiorek D. P. Automatic configuration of embedded multicomputer systems. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1998) 17(2):84–95Crossref, Google Scholar
• Czarnecki R., Deniziak S., Sapiecha K. An iterative improvement co-synthesis algorithm for optimization of SOPC architecture with dynamically reconfigurable FPGAs. Proc. Euromicro Sympos. Digital System Design (2003) Belek-Antalya, Turkey:443–446Crossref, Google Scholar
• Dick R. P., Jha N. K. CORDS: Hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. Proc. 1998 IEEE/ACM Internat. Conf. Comput.-Aided Design (1998a) San Jose, California:62–67Crossref, Google Scholar
• Dick R. P., Rhodes D. L., Wolf W. TGFF: Task graphs for free. Proc. Internat. Workshop Hardware/Software Codesign (1998b) Seattle, Washington:97–101Crossref, Google Scholar
• El-Rewini H., Lewis T. T. Scheduling parallel program tasks onto arbitrary target machines. J. Parallel Distributed Comput. (1990) 9(2):138–153Crossref, Google Scholar
• Hadj-Alouane A. B., Bean J. C., Murty K. G. A hybrid genetic/optimization algorithm for a task allocation problem. J. Scheduling (1999) 2(4):189–201Crossref, Google Scholar
• Hanson J. M., Shrader M. W., Chang H. P., Freeman S. E. Guidance and dispersion Studies of national launch system ascent trajectories. Proc. 1992 AIAA Guidance Control Conf. (1992) Crossref, Google Scholar
• Hauck S. The roles of FPGAs in reprogrammable systems. Proc. IEEE (1998) 86(4):615–638Crossref, Google Scholar
• Intel Intel VTune Performance Analyzer. (2004) . http://www.intel.comGoogle Scholar
• Holland J.Adaptation in natural and artificial systems (1975) (University of Michigan, Ann Arbor, MI) Google Scholar
• Hwang K.Advanced Computer Architecture Parallelism Scalability Programmability (1993) (McGraw-Hill, New York) Google Scholar
• Loo S. M. Static scheduling in a reconfigurable hardware environment. (2003) . Unpublished doctoral dissertation, Dissertation. University of Alabama, Huntsville, AlabamaGoogle Scholar
• Loo S. M. Reconfigurable system design model webpage. (2004) . http://coen.boisestate.edu/smloo/rsdmGoogle Scholar
• Noguera J., Badia R. M. Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. Proc. 10th Internat. Sympos. Hardware/Software Codesign (2002a) Estes Park, CO:205–210Crossref, Google Scholar
• Noguera J., Badia R. M. HW/SW codesign techniques for dynamically reconfigurable architectures. IEEE Trans. Very Large Scale Integration Systems (2002b) 10(4):399–415Crossref, Google Scholar
• OCPIP (Open Core Protocol Specification, 2.0 Release Candidate) OCP international partnership. (2004) . http://www.ocp-ip.orgGoogle Scholar
• Otter M., Elmqvist H., Cellier F. E. Modeling of multibody systems with the object-oriented modeling language dymola. Nonlinear Dynamics (1996) 9:91–112Crossref, Google Scholar
• Ravi S., Jha N. K. Test synthesis of systems-on-a-chip. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2002) 21(10):1211–1217Crossref, Google Scholar
• Reconfigurable System Design Model (2004) . http://coen.boisestate.edu/smloo/rsdmGoogle Scholar
• Shang L., Jha N. K. Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs. 15th IEEE Internat. Conf. VLSI Design (VLSI) (2002) Bangalore, India:345–352Crossref, Google Scholar
• Stankovic J. A., Spuri M., Natale M. D., Buttazzo G. Implications of classical results for real-time systems. IEEE Trans. Comput. (1995) 28(6):16–25Google Scholar
• Tobita T., Kasahara H. A standard task graph set for fair evaluation of multiprocessor scheduling algorithms. J. Scheduling (2002) 5:379–394Crossref, Google Scholar
• Vallerio K. S., Jha N. K. Task graph extraction for embedded system synthesis. Proc. Internat. Conf. VLSI Design (2003) New Delhi, India:480–486Crossref, Google Scholar
• Vallerio K. S., Jha N. K. Task graph transformation to aid system synthesis. Proc. Internat. Conf. Circuits Systems (2002) Phuket, Thailand:695–698Crossref, Google Scholar
• Wells B. E. A hard real-time static task allocation methodology for highly-constrained message-passing environments. Internat. J. Comput. Their Appl. (1995) 2(3):123–136Google Scholar
• Wells B., E K. G., Ricks, Weir J. M. Parallel simulation of a large scale aerospace system in a multicomputer environment. IEEE Trans. Aerospace Electronic Systems (1997) 33(2):507–522Crossref, Google Scholar
• Wolf W. A decade of hardware/software codesign. IEEE Comput. Magazine (2003) 36(4):38–43Crossref, Google Scholar
• Xilinx (2002) . Xilinx Virtex-E 1.8V Extended Memory FPGA. DS 025 http://www.xilinx.comGoogle Scholar
• Xilinx (2003a) . Xilinx Virtex-II Pro Platform FPGA Data Sheet, DS 081 http://www.xilinx.comGoogle Scholar
• Xilinx Xilinx Virtex-II Platform FPGA Data Sheet. DS 031. (2003b) . http://www.xilinx.comGoogle Scholar
• Xilinx (2004) . Xilinx Online Device Data Sheets http://www.xilinx.comGoogle Scholar
• Xilinx MicroBlaze (2004) . http://www.xilinx.com/microblazeGoogle Scholar