Digital Circuit Optimization via Geometric Programming
Published Online:1 Dec 2005https://doi.org/10.1287/opre.1050.0254
References
- Fitted Elmore delay: A simple and accurate interconnect delay model. IEEE Trans. VLSI Systems (2004) 12(7):691–696Crossref, Google Scholar
- Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2003) 22(9):1243–1260Crossref, Google Scholar
- RC delay metrics for performance optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2001a) 20(5):571–582Crossref, Google Scholar
- Interconnect synthesis without wire tapering. Integration, the VLSI J. (2001b) 20:90–114Google Scholar
- Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2004) 23(1):136–141Crossref, Google Scholar
- Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. IEEE Trans. Very Large Scale Integration (VLSI)Systems (2002) 10(2):71–78Crossref, Google Scholar
- Design and optimization of multithreshold CMOS (MTCMOS) circuits. IEEE Trans. Comput.-Aided Design of Integrated Circuits Systems (2003) 22(10):1324–1342Crossref, Google Scholar
- A multivariate approach to estimating the completion time for PERT networks. J. Oper. Res. Soc. (1986) 37:811–815Crossref, Google Scholar
- Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI. IEEE Trans. Electron Devices (1997) 44(3):414–422Crossref, Google Scholar
- Combining dual-supply, dual-threshold and transistor sizing for power reduction. Proc. IEEE Internat. Conf. Comput. Design: VLSI in Computers and Processors (2002a) (Cambridge, MA)316–321Crossref, Google Scholar
- Reducing power with dual-supply, dual-thresholds and transistor sizing. Proc. IEEE Internat. Conf. Comput. Design: VLSI in Computers and Processors (2002b) (Cambridge, MA)16–18Crossref, Google Scholar
- Supply voltage scaling for temperature insensitive CMOS circuit operation. IEEE Trans. Circuits Systems II: Analog and Digital Signal Processing (1998) 45(3):415–417Crossref, Google Scholar
- Speed and power scaling of SRAMs. IEEE J. Solid-State Circuits (2000) 35(2):175–185Crossref, Google Scholar
- TAU: Timing analysis under uncertainty. Internat. Conf. Comput.-Aided Design (2003) San Jose, CA:615–620Google Scholar
- Slope propagation in static timing analysis. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2002) 21(10):1180–1195Crossref, Google Scholar
- A fast algorithm for minimizing the Elmore delay to identified critical sinks. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1997) 16(7):753–759Crossref, Google Scholar
- Efficient estimation of arc criticalities in stochastic activity networks. Management Sci. (1995) 41(1):58–67Link, Google Scholar
- A circuit-level perspective of the optimum gate oxide thickness. IEEE Trans. Electron Devices (2001) 48(8):1800–1810Crossref, Google Scholar
- Convex Optimization (2004) (Cambridge University Press, Cambridge, UK) Crossref, Google Scholar
- A tutorial on geometric programming. Optim. Engrg. (2004) . Forthcoming. Available from www.stanford.edu/boyd/~gp_tutorial.htmlGoogle Scholar
- Statistical method for the analysis of interconnects delay in submicrometer layouts. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2001) 20(8):957–966Crossref, Google Scholar
- Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE (2001) 89(3):341–365Crossref, Google Scholar
- A leakage reduction methodology for distributed MTCMOS. IEEE J. Solid-State Circuits (2004) 39(5):818–826Crossref, Google Scholar
- Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2003) 22(3):346–351Crossref, Google Scholar
- Minimizing power consumption in digital CMOS circuits. Proc. IEEE (1995) 83(4):498–523Crossref, Google Scholar
- Energy minimization using multiple supply voltages. IEEE Trans. Very Large Scale Integration Systems (1997) 5(4):436–443Crossref, Google Scholar
- Simultaneous voltage scaling and gate sizing for low-power design. IEEE Trans. Circuits Systems II: Analog and Digital Signal Processing (2002) 49(6):400–408Crossref, Google Scholar
- On gate level power optimization using dual-supply voltages. IEEE Trans. Very Large Scale Integration Systems (2001) 9(5):616–629Crossref, Google Scholar
- Greedy wire-sizing is linear time. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1999) 18(4):398–405Crossref, Google Scholar
- Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. Comput.-Aided Design of Integrated Circuits Systems (1999) 18(7):1014–1025Crossref, Google Scholar
- Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects. IEEE Trans. Electron Devices (1997) 44(11):1951–1957Crossref, Google Scholar
- Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integration Systems (2004) 12(1):28–41Crossref, Google Scholar
- Simultaneous gate sizing and placement. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2000) 19(2):206–214Crossref, Google Scholar
- An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1999) 18(9):1297–1304Crossref, Google Scholar
- Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Automation of Electronic Systems (2001a) 6(3):343–371Crossref, Google Scholar
- VLSI circuit performance optimization by geometric programming. Ann. Oper. Res. (2001b) 105:37–60Crossref, Google Scholar
- Optimization of phase-locked loop circuits via geometric programming. Proc. Custom Integrated Circuits Conf. (CICC) (2003) Orlando, FL:326–328Crossref, Google Scholar
- Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1999) 18(4):406–420Crossref, Google Scholar
- Optimal wire sizing for interconnects with multiple sources. ACM Trans. Design Automation Electronic Systems (1996) 1(4):478–511Crossref, Google Scholar
- Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integration Systems (1994) 2(4):408–423Crossref, Google Scholar
- Optimal wiresizing under Elmore delay model. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1995) 14(3):321–336Crossref, Google Scholar
- Wire width planning for interconnect performance optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2002) 21(3):319–329Crossref, Google Scholar
- Performance optimization of VLSI interconnect layout. Integration, the VLSI J. (1996) 21:1–94Crossref, Google Scholar
- Resource allocation in project network models—A survey. J. Indust. Engrg. (1966) 17(4):77–187Google Scholar
- Optimal allocation of local feedback in multistage amplifiers via geometric programming. IEEE Trans. Circuits Systems I (2001) 48(1):1–11Crossref, Google Scholar
- Inequalities for the completion times of stochastic PERT networks. Math. Oper. Res. (1979) 4(4):441–447Link, Google Scholar
- Determining the K most critical paths in PERT networks. Oper. Res. (1984) 32:859–877Link, Google Scholar
- Transistor sizing: How to control the speed and energy consumption of a circuit. Proc. 10th Internat. Sympos. Asynchronous Circuits Systems (2004) Crete, Greece:51–61Crossref, Google Scholar
- Some Network Models in Management Science (1970) (Springer-Verlag, New York) Crossref, Google Scholar
- Project Planning and Control by Network Models (1977) (John Wiley and Sons, New York) Google Scholar
- The transient response of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. (1948) 19(1):55–63Crossref, Google Scholar
- TILOS: A posynomial programming approach to transistor sizing. IEEE Internat. Conf. Comput.-Aided Design: ICCAD-85. Digest Tech. Papers (1985) (IEEE Computer Society Press, Santa Clara, CA) 326–328Google Scholar
- Shaping a distributed-RC line to minimize Elmore delay. IEEE Trans. Circuits Systems I: Fundamental Theory Appl. (1995) 42(12):1020–1022Crossref, Google Scholar
- Optimal shape function for a bidirectional wire under Elmore delay model. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1999) 18(7):994–999Crossref, Google Scholar
- The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. Comput.-Aided Design of Integrated Circuits Systems (1997) 16(1):95–104Crossref, Google Scholar
- A statistical theory for PERT critical path analysis. Management Sci. (1966) 12(6):469–481Link, Google Scholar
- Automated optimal design of switched-capacitor filters. Design, Automation and Test in Europe Conference and Exhibition (2002) Paris, France:1111Crossref, Google Scholar
- Design of pipeline analog-to-digital converters via geometric programming. Proc. IEEE/ACM Internat. Conf. Comput. Aided Design (2002) San Jose, CA:317–324Google Scholar
- Analog design space exploration: Efficient description of the design space of analog circuits. Proc. 40th Design Automation Conf. (2003) Anaheim, CA:970–973Crossref, Google Scholar
- GPCAD: A tool for CMOS op-amp synthesis. Proc. IEEE/ACM Internat. Conf. Comput. Aided Design (1998) San Jose, CA:296–303Google Scholar
- Design and optimization of LC oscillators. Proc. IEEE/ACM Internat. Conf. Comput.-Aided Design (1999) San Jose, CA:65–69Crossref, Google Scholar
- The future of wires. Proc. IEEE (2001) 89(4):490–504Crossref, Google Scholar
- Analysis and Design of Digital Integrated Circuits (2004) 3rd ed.(McGraw-Hill, New York) Google Scholar
- (1984) (Timing models for MOS circuits). Ph.D. thesis, Stanford University, Stanford, CAGoogle Scholar
- Total power optimization through simultaneously multiple-Vdd multiple-Vth assignment and device sizing with stack forcing. Proc. Internat. Sympos. Low Power Electronics and Design (ISLPED) (2004) Newport Beach, CA:144–149Crossref, Google Scholar
- VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2003) 11(5):755–761Crossref, Google Scholar
- Level conversion for dual-supply systems. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2004) 12(2):185–195Crossref, Google Scholar
- Equivalent Elmore delay for RLC trees. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2000) 19(7):83–97Crossref, Google Scholar
- Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2000) 19(9):999–1010Crossref, Google Scholar
- Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2002) 10(1):1–5Crossref, Google Scholar
- Noise constrained power optimization for dual Vt domino logic. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2003) 10(5):532–541Crossref, Google Scholar
- Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Systems (1993) 1(2):126–137Crossref, Google Scholar
- An analytical delay model for RLC interconnects. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1997) 16(12):1507–1514Crossref, Google Scholar
- A 175mv multiply-accumulate unit using an adaptive supply voltage and body bias architecture. IEEE J. Solid-State Circuits (2002) 37(11):1545–1554Crossref, Google Scholar
- Dual-threshold voltage techniques for low-power digital circuits. IEEE J. Solid-State Circuits (2000) 35(7):1009–1018Crossref, Google Scholar
- Total power optimization by simultaneous dual-Vth allocation and device sizing in high performance microprocessors. Proc. 39th IEEE/ACM Design Automation Conf. (2002) New Orleans, LA:486–491Google Scholar
- A new class of convex functions for delay modeling and its application to the transistor sizing problem. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2000) 19(7):779–788Crossref, Google Scholar
- Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2004) 23(4):509–516Crossref, Google Scholar
- EWA: Efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1998) 17(1):40–49Crossref, Google Scholar
- Standby power optimization via transistor sizing and dual threshold voltage assignment. Proc. IEEE/ACM Internat. Conf. Comput.-Aided Design (2002) San Jose, CA:375–378Crossref, Google Scholar
- Energy efficient skewed static logic design with dual Vth: Design and synthesis. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2003a) 11(1):64–70Crossref, Google Scholar
- Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2003b) 11(5):879–887Crossref, Google Scholar
- A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing. (2004) . Submitted to Optim. Engrg. Available from www.stanford.edu/boyd/heur_san_opt.htmlGoogle Scholar
- Bounding distribution for stochastic acyclic networks. Oper. Res. (1971) 19:1586–1601Link, Google Scholar
- CAD for nanometer silicon design challenges and success. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2004) 12(11):1132–1147Crossref, Google Scholar
- Exploring the design space of mixed swing quadrail for low-power digital circuits. IEEE Trans. Very Large Scale Integration Systems (1997) 5(4):389–400Crossref, Google Scholar
- High performance level conversion for dual Vdd design. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2004) 12(9):926–936Crossref, Google Scholar
- Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. Very Large Scale Integration Systems (2004) 12(2):155–166Crossref, Google Scholar
- Optimal wire-sizing function under the Elmore delay model with bounded wire sizes. IEEE Trans. Circuits Systems I: Fundamental Theory Appl. (2002) 49(11):1671–1677Crossref, Google Scholar
- RC(L) interconnect sizing with second order considerations via posynomial programming. Proc. ACM/SIGDA Internat. Sympos. Physical Design (2001) Sonoma, CA:16–21Crossref, Google Scholar
- Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages. IEEE J. Solid-State Circuits (1999) 34(1):85–89Crossref, Google Scholar
- Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation. Proc. Internat. Sympos. Low Power Electronics and Design (ISLPED) (2004) Newport Beach, CA:2–7Crossref, Google Scholar
- Concurrent logic restructuring and placement for timing closure. Proc. IEEE/ACM Internat. Conf. Comput.-Aided Design (1999) San Jose, CA:31–35Google Scholar
- Dynamic frequency scaling with buffer insertion for mixed workloads. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2002) 21(11):1284–1305Crossref, Google Scholar
- A computational study on bounding the makespan distribution in stochastic project networks. Ann. Oper. Res. (2001) 102:49–64Crossref, Google Scholar
- CMOS op-amp sizing using a geometric programming formulation. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2001) 20(1):22–38Crossref, Google Scholar
- Methods for true energy-performance optimization. IEEE J. Solid-State Circuits (2004) 39(8):1282–1293Crossref, Google Scholar
- Macromodeling and optimization of digital MOS VLSI circuits. IEEE Trans. Comput.-Aided Design Integrated Circuits and Systems (1986) 5(4):659–678Crossref, Google Scholar
- Globally optimal floorplanning for a layout problem. IEEE Trans. Circuits Systems I: Fundamental Theory Appl. (1996) 43(29):713–720Google Scholar
- Simple accurate expressions for planar spiral inductances. IEEE J. Solid-State Circuit (1999) 34(10):1419–1424Crossref, Google Scholar
- Bandwidth extension in CMOS with optimized on-chip inductors. IEEE J. Solid-State Circuits (2000) 35(3):346–355Crossref, Google Scholar
- Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integration (VLSI) Systems (2003) 11(4):716–730Crossref, Google Scholar
- Interior-Point Polynomial Methods in Convex Programming (1994) 13(Studies in Applied Mathematics. SIAM, Philadelphia, PA) Crossref, Google Scholar
- Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. Proc. Internat. Sympos. Low Power Electronics and Design (ISLPED) (2003) Seoul, Korea:158–163Crossref, Google Scholar
- Numerical Optimization (1999) (Springer Series in Operations Research. Springer, New York) Crossref, Google Scholar
- A general probabilistic framework for worst case timing analysis. Proc. 39th IEEE/ACM Design Automation Conf. (2002) New Orleans, LA:556–561Crossref, Google Scholar
- Direct sampling methodology for statistical analysis of scaled CMOS technologies. IEEE Trans. Semiconductor Manufacturing (1999) 12(4):403–408Crossref, Google Scholar
- Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits. IEEE Trans. Very Large Scale Integration Systems (2001) 9(2):390–394Crossref, Google Scholar
- Theory and algorithm of local refinement based optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1998) 18(4):406–420Google Scholar
- A new method for robust design of digital circuits. Proc. Internat. Sympos. Quality Electronic Design (ISQED) (2005) San Jose, CA:676–681Crossref, Google Scholar
- GP based transistor sizing for optimal design of nanoscale CMOS inverter. IEEE Conf. Nanotechnology (2003) San Francisco, CA:524–527Crossref, Google Scholar
- Power minimization in IC design: Principles and applications. ACM Trans. Design Automation of Electronic Systems (1996) 1(1):3–56Crossref, Google Scholar
- Matching properties of MOS transistors. IEEE J. Solid State Circuits (1989) 24(5):1433–1439Crossref, Google Scholar
- Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1990) 9(4):352–366Crossref, Google Scholar
- Realizable parasitic reduction using generalized Y-Δ transformation. Proc. 40th IEEE/ACM Design Automation Conf. (2003) Anaheim, CA:220–225Crossref, Google Scholar
- Digital Integrated Circuits: A Design Perspective (2002) 2nd ed.(Prentice-Hall, Englewood Cliffs, NJ) Google Scholar
- A fanout optimization algorithm based on the effort delay model. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2003) 22(12):1671–1678Crossref, Google Scholar
- The completion times of PERT networks. Oper. Res. (1976) 25:15–29Link, Google Scholar
- Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE (2003) 91(2):305–327Crossref, Google Scholar
- Signal delay in RC tree networks. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1983) 2(3):202–211Crossref, Google Scholar
- Approximation of wiring delay in MOSFET LSI. IEEE J. Solid-State Circuits (1988) 18(4):418–426Crossref, Google Scholar
- Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits (1990) 25(2):584–593Crossref, Google Scholar
- Optimal design of macrocells for low power and high speed. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1996) 15(9):1160–1166Crossref, Google Scholar
- Wire sizing as a convex optimization problem: Exploring the area-delay tradeoff. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1996) 15:1001–1011Crossref, Google Scholar
- Power-delay optimization in gate sizing. ACM Trans. Design Automation of Electronic Systems (2000) 5(1):98–114Crossref, Google Scholar
- An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1993) 12(11):1621–1634Crossref, Google Scholar
- Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1998) 17(2):173–182Crossref, Google Scholar
- Delay-optimized implementation of IEEE floating-point addition. IEEE Trans. Comput. (2004) 53(2):97–113Crossref, Google Scholar
- Optimization-based transistor sizing. IIEEE J. Solid-State Circuits (1988) 23(2):400–409Crossref, Google Scholar
- Power conscious CAD tools and methodologies: A perspective. Proc. IEEE (1995) 83(4):570–594Crossref, Google Scholar
- Duet: An accurate leakage estimation and optimization tool for dual-Vth circuits. IEEE Trans. Very Large Scale Integration Systems (2002) 10(2):79–90Crossref, Google Scholar
- Low-power design using multiple channel lengths and oxide thicknesses. IEEE Design Test Comput. (2004) 21(1):56–63Crossref, Google Scholar
- Minimizing total power by simultaneous Vdd/Vth assignment. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2004) 23(5):665–677Crossref, Google Scholar
- Logical Effort: Designing Fast CMOS Circuits (1999) (Morgan Kaufmann Publishers, San Francisco, CA) Google Scholar
- Analytical modeling and characterization of deep submicron interconnect. Proc. IEEE (2001) 89(5):634–666Crossref, Google Scholar
- 1GHz fully pipelined 3.7ns address access time 8k 1024 embedded DRAM macro. ISSCC Digest of Tech. Papers (2000) San Francisco, CA:396–397Google Scholar
- Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid-State Circuits (2003) 38(11):1838–1845Crossref, Google Scholar
- Clustered voltage scaling technique for low-power design. Proc. 1995 Internat. Sympos. Low Power Design (1995) San Diego, CA:3–8Crossref, Google Scholar
- Monte Carlo methods and the PERT problem. Oper. Res. (1963) 11:839–860Link, Google Scholar
- Automated design of operational transconductance amplifiers using reversed geometric programming. Proc. 41st IEEE/ACM Design Automation Conf. (2004) (IEEE/ACM, San Diego, CA) 133–138Crossref, Google Scholar
- Low-power buffered clock tree design. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (1997) 16(9):965–975Crossref, Google Scholar
- Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integration Systems (1999) 7(1):16–24Crossref, Google Scholar
- CMOS VLSI Design (2004) 3rd ed.(Addison Wesley, Boston, MA) Google Scholar
- ORACLE: Optimization with recourse of analog circuits including layout extraction. Proc. 41st IEEE/ACM Design Automation Conf. (2004) (IEEE/ACM, San Diego, CA) 151–154Crossref, Google Scholar
- Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices (1997) 44(5):822–831Crossref, Google Scholar
- A comparative study of gate direct tunneling and drain leakage currents in N-MOSFETs with sub-2100-nm gate oxides. IEEE Trans. Electronic Devices (2000) 47(8):1636–1644Crossref, Google Scholar
- Interior Point Algorithms: Theory and Analysis (1997) (Wiley-Interscience Series in Discrete Mathematics and Optimization, Wiley, New York) Crossref, Google Scholar
- Converter-free multiple-voltage scaling techniques for low-power CMOS digital design. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2001) 20(1):172–176Crossref, Google Scholar
- Handling soft modules in general nonslicing floorplan using Lagrangian relaxation. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems (2001) 20(5):687–692Crossref, Google Scholar

